As opposed to planar complementary metal oxide semiconductor (CMOS) devices, vertical field effect transistors (VFETs) are oriented with a vertical fin channel disposed on a bottom source and drain, and a top source and drain disposed on the fin channel. Following fabrication of the VFET device, top contacts are often formed to the top and bottom source and drains. VFETs are being explored as a viable device option for continued CMOS scaling beyond the 7 nanometer (nm) technology node.
Top contact resistance (Rc) is an important factor in VFET device performance. For instance, top contact resistance can impact the switching characteristics of the device.
Accordingly, techniques for accurately and effectively determining top contact resistance in a VFET device would be desirable.